Any digital microcircuits are built on the basis of the simplest logical elements:

Let's take a closer look at the design and operation of digital logic elements.

Inverter

The simplest logic element is an inverter, which simply changes the input signal to the exact opposite value. It is written in the following form:

where the bar is over the input value and denotes a change to its opposite. The same action can be written using given in Table 1. Since the inverter has only one input, its truth table consists of only two lines.

Table 1. Truth table of the inverter logic element

In	Out
0	1
1	0

As a logical inverter, you can use a simple amplifier with a transistor connected across (or a source for a field-effect transistor). The schematic diagram of the inverter logic element, made on a bipolar n-p-n transistor, is shown in Figure 1.

Figure 1. Circuit of the simplest logic inverter

Logic inverter chips can have different signal propagation times and can operate on different types of loads. They can be made on one or several transistors. The most common logic elements are made using TTL, ESL and CMOS technologies. But regardless of the logic element circuit and its parameters, they all perform the same function.

In order to ensure that the features of switching on transistors do not obscure the function being performed, special symbols for logical elements were introduced - conventional graphic symbols. inverter is shown in Figure 2.

Figure 2. Graphic designation of a logical inverter

Inverters are present in almost all series of digital microcircuits. In domestic microcircuits, inverters are designated by the letters LN. For example, the 1533LN1 chip contains 6 inverters. Foreign microcircuits use a digital designation to indicate the type of microcircuit. An example of a chip containing inverters is the 74ALS04. The name of the microcircuit reflects that it is compatible with TTL microcircuits (74), is manufactured using improved low-power Schottky technology (ALS), and contains inverters (04).

Currently, surface-mount microcircuits (SMD microcircuits) are more often used, which contain one logical element, in particular an inverter. An example is the SN74LVC1G04 chip. The microcircuit is manufactured by Texas Instruments (SN), is compatible with TTL microcircuits (74), is manufactured using low-voltage CMOS technology (LVC), contains only one logic element (1G), which is an inverter (04).

To study the inverting logic element, you can use widely available radio-electronic elements. Thus, ordinary switches or toggle switches can be used as an input signal generator. To study the truth table, you can even use a regular wire, which we will alternately connect to a power source and a common wire. A low-voltage light bulb or LED connected in series with a current-limiting one can be used as a logic probe. A schematic diagram of the study of the logical element of the inverter, implemented using these simple radio-electronic elements, is shown in Figure 3.

Figure 3. Logic inverter study diagram

The diagram for studying a digital logic element, shown in Figure 3, allows you to visually obtain data for the truth table. A similar study is carried out in More complete characteristics of the digital logic element of the inverter, such as the delay time of the input signal, the rate of rise and fall of the output signal edges, can be obtained using a pulse generator and an oscilloscope (preferably a two-channel oscilloscope).

Logic gate "AND"

The next simplest logical element is a circuit that implements the logical multiplication operation "AND":

F(x 1 ,x 2) = x 1 ^x 2

where the symbol ^ and denotes the logical multiplication function. Sometimes the same function is written in a different form:

F(x 1 ,x 2) = x 1 ^x 2 = x 1 ·x 2 = x 1 &x 2 .

The same action can be written using the truth table given in Table 2. The formula above uses two arguments. Therefore, the logic element that performs this function has two inputs. It is designated "2I". For a logical element "2I" the truth table will consist of four rows (2 2 = 4).

Table 2. Truth table of logical element "2I"

In1	In2	Out
0	0	0
0	1	0
1	0	0
1	1	1

As can be seen from the above truth table, an active signal at the output of this logic element appears only when there are ones at both the X and Y inputs. That is, this logical element really implements the “AND” operation.

The easiest way to understand how a 2I logic element works is with a circuit built on idealized electronically controlled switches, as shown in Figure 2. In the circuit diagram shown, current will flow only when both switches are closed, and therefore , a unity level at its output will appear only with two units at the input.

Figure 4. Schematic diagram of a logical element "2I"

A conditional graphical representation of a circuit that performs the logical function “2I” on circuit diagrams is shown in Figure 3, and from now on, circuits that perform the “AND” function will be shown in exactly this form. This image does not depend on the specific circuit diagram of the device that implements the logical multiplication function.

Figure 5. Symbolic graphical representation of the logical element "2I"

The function of logical multiplication of three variables is described in the same way:

F(x 1 ,x 2 ,x 3)=x 1 ^x 2 ^x 3

Its truth table will already contain eight rows (2 3 = 4). The truth table of the three-input logical multiplication circuit "3I" is given in Table 3, and the conditional graphical representation is in Figure 4. In the circuit of the logical element "3I", built according to the principle of the circuit shown in Figure 2, you will have to add a third key.

Table 3. Truth table of a circuit performing the logical function "3I"

In1	In2	In3	Out
0	0	0	0
0	0	1	0
0	1	0	0
0	1	1	0
1	0	0	0
1	0	1	0
1	1	0	0
1	1	1	1

A similar truth table can be obtained using a 3I logic element study circuit similar to the logic inverter study circuit shown in Figure 3.

Figure 6. Symbolic graphic designation of a circuit that performs the logical function "3I"

Logic element "OR"

The next simplest logical element is a circuit that implements the logical addition operation "OR":

F(x 1 ,x 2) = x 1 Vx 2

where the symbol V denotes the logical addition function. Sometimes the same function is written in a different form:

F(x 1 ,x 2) = x 1 Vx 2 = x 1 +x 2 = x 1 |x 2 .

The same action can be written using the truth table given in Table 4. The formula above uses two arguments. Therefore, the logic element that performs this function has two inputs. Such an element is designated "2OR". For the "2OR" element, the truth table will consist of four rows (2 2 = 4).

Table 4. Truth table of the logical element "2OR"

In1	In2	Out
0	0	0
0	1	1
1	0	1
1	1	1

As in the case considered for , we will use keys to implement the “2OR” scheme. This time we will connect the keys in parallel. The circuit that implements truth table 4 is shown in Figure 5. As can be seen from the above circuit, the logical one level will appear at its output as soon as any of the keys is closed, that is, the circuit implements the truth table shown in Table 4.

Figure 7. Schematic diagram of a 2OR logic element

Since the logical summation function can be implemented by various circuit diagrams, a special symbol “1” is used to indicate this function on circuit diagrams, as shown in Figure 6.

Figure 6. Symbolic graphical representation of a logical element performing the “2OR” function

Last file update date: 03/29/2018

Literature:

With the article "logical elements" read:

Any logic circuit without memory is completely described by a truth table... To implement a truth table, it is enough to consider only those rows...
http://site/digital/SintSxem.php

Decoders (decoders) allow you to convert some types of binary codes into others. For example...
http://site/digital/DC.php

Quite often, digital equipment developers are faced with the opposite problem. You need to convert octal or decimal linear code to...
http://site/digital/Coder.php

Multiplexers are devices that allow you to connect multiple inputs to one output...
http://site/digital/MS.php

Demultiplexers are devices... A significant difference from a multiplexer is...
http://site/digital/DMS.php

Logic circuit is a schematic representation of a device consisting of switches and the conductors connecting them, as well as inputs and outputs to which an electrical signal is supplied and removed.

Each switch has only two states: closed and open. We associate switch X with a logical variable x, which takes the value 1 if and only if switch X is closed and the circuit conducts current; if the switch is open, then x is zero.

Two circuits are said to be equivalent if current passes through one of them if and only if it passes through the other (given the same input signal).

Of two equivalent circuits, the simpler circuit is the one whose conductance function contains a smaller number of logical operations or switches.

When considering switching circuits, two main tasks arise: synthesis and analysis of the circuit.

SYNTHESIS OF THE SCHEME according to the given conditions of its operation is reduced to the following three stages:

1. compiling a conductivity function using a truth table reflecting these conditions;

2. simplifying this function;

3. constructing an appropriate diagram.

SCHEME ANALYSIS comes down to:

1. determining the values ​​of its conductivity function for all possible sets of variables included in this function.

2. obtaining a simplified formula.

Construction of logical circuits

As a rule, the construction and calculation of any circuit is carried out starting from its output. Let's say we're given a Boolean expression:

F = BA + B A + C B.

First stage: logical addition, logical OR operation is performed, considering the functions B A, B A and C B as input variables:

Second stage: logical AND elements are connected to the inputs of the OR element, the input variables of which are already A, B, C and their inversions:

Third stage: to obtain inversions A and B, inverters are installed at the corresponding inputs:

B 1 B&

This construction is based on the following feature: since the values ​​of logical functions can only be zeros and ones, any logical functions can be represented as arguments to other more complex functions. Thus, the construction of a logical circuit is carried out from output to input.

2.1 Basic definitions

Electronic circuits built only on logic are called combinational. The output or outputs depend only on the combination of variables at the inputs.

In contrast to the same circuits containing memory elements (for example, flip-flops), which are called sequential. Sequential, since the output(s) depend not only on the combination of variables, but also on the state of the memory elements (the sequence of writing to them).

There are three main types of logical elements: 1 Perform an addition operation (adder). Disjunction.

			F = x1 + x2
							F = x1 + x 2 + ... + x n

2 Perform a multiplication operation. Conjunction.

F = x1 x 2 ... x n

						F = x1 x2

3 Perform negation.

F=x

Logical elements that implement these operations are called simplest, and those that contain several simplest ones are called combined.

Most of the logical elements of addition and multiplication are performed with negation. Their typical characteristics in static mode are shown in Figure 2.1.

U pom+ U pom−

Figure 2.1 – Static characteristics of logical elements with negation

U pom + – interference that takes the logic element out of a stable state

M to the beginning of the active region at point A (see Figure 2.1).

U pom - is an interference that removes N from a stable state at the foot of the active region of point B.

U is the active region, the operating point in this region moves abruptly,

And Most logic elements have a time limit for the operating point to be in this area. Inside, between points A and B, only radio amateurs can set the operating point.

Depending on the digital values ​​U pom +, U pom −, three types of logic circuits are distinguished:

- low noise immunity (0.3÷0.4 fractions of a volt);

- average noise immunity (0.4÷1 V);

- high noise immunity (above 1 V).

TO circuits with high noise immunity include diode logic circuits (up to several kV); machine logic (10÷15 V); complementary logic CMOS (6÷8 V).

Based on performance, there are four types:

- Latency time less than 5 ns – ultra-fast;

- 5÷10 ns – high-speed logic;

- 10÷50 ns – low speed;

- more than 50 ns – slow-acting logic circuits.

An important parameter is power consumption.

1 Micropower logic circuits range from one to tens of microwatts per package. Usually this CMOS logic (see CMOS switches) or logic with injection power.

2 Logic with average power consumption from one to tens of mW per package. Usually this TTL logic.

3 Logic with high power consumption (hundreds of mW per package).

Previously, there was a tendency: the higher the consumption, the higher the speed, because the elements of transistors of various types switch most quickly in the active region (in this area the highest consumption).

Highlight

– diode logic circuits (the simplest);

– transistor-transistor(TTL logic);

– emitter-connected logic (ESL) is a type of TTL, the difference is in the emitter connections, mode and negative power supply, therefore the logic is also called negative in contrast to the positive logic TTL (+2...5V). To connect and coordinate them with each other, PU matching circuits are used (level converters K500, PU124, PU125, K176 PU1, PU10).

– logic with injection power AND 2 L – a type of TTL logic (I2 – integrated with injection power).

– CMOS logic is a type of TTL, but on UTs of different types of conductivity.

– OPTL - (optocoupler connections, transistor logic) provides galvanic isolation.

– PTS logic using Schottky field-effect transistors.

– logical matrices.

According to the temperature reserve, they distinguish

– microcircuits of wide application with a temperature range-10°С…+70°С

– microcircuits for special applications-60°С… +125°С

Also distinguished by the number of inputs and load capacity

– with a small number of inputs m to ten

– with a large number of inputs - over ten

– with a low load capacity n equal to one.

Load capacity refers to the number of similar logic circuits that can be connected to the output of exactly the same logic circuit. Passive logic circuits have low load capacity.

– with an average load capacity of n to ten

– with high load capacity n>10

2.2 Diode logic circuits

These are the simplest circuits and have the highest noise immunity. The number of inputs reaches ten on average. The load is usually one element. This means that the load is exactly the same LE. Low load capacity because these circuits are passive, there are no power amplifiers. The frequency range is low (up to 1 MHz), since combined parallel diode inputs are equivalent to combining parallel capacitors that charge and discharge. This takes time and reduces performance.

Figure 2.2 shows a diode logic addition circuit.

Figure 2.2 – Diode logic addition circuit

There are two possible states:

1 The inputs are connected to ground through open outputs of the same logic circuits. This condition is sometimes taken to be equivalent to connecting all inputs to ground through conductors.

2 In order to open the diodes, it is necessary to apply a voltage whose level is several times greater than the dead zone of the diodes.

5 V is the minimum standard voltage, but it can be 500 V and 5 kV if the diodes are high voltage. In this case, the load capacity may be greater than unity, but the consumption of circuits becomes large.

The scheme works as follows. We assume that a high voltage level, called one, is supplied to input X1. This level must come from the output of exactly the same logic circuit, or in some other way that simulates the same conditions. But since one is supplied only to input X1, then the remaining inputs X2...Xn must have zeros. They must also be organized by outputs of the same logical circuits. In the simplest case, these can be conductors (jumpers) connecting inputs X2...Xn to ground. Consequently, the diode VD1 will be open, the high level of X1 passes through VD1 to the output, at which this high level is also allocated, from which the voltage drop across the diode is subtracted. Those. the output will have a smaller high level, however, it is called one. Diodes VD2...VDn will be closed at this time, since the inputs X2...Xn have low levels, their barrier capacitances are connected in parallel and accumulate charge.

If you now apply a high level to input X2, then VD2 will open but the state of output F will hardly change, i.e. there remains a high level - one. The same thing will happen if one is applied to all inputs simultaneously. Thus, the logical addition operation is satisfied.

The principle of duality here is that if the low levels at the inputs and at the output are called ones, then this addition logic circuit will perform the logical multiplication operation (see Figure 2.2).

LOGIC ELEMENTS

General information.

It was noted above that logical functions and their arguments take the value log.0 and log.1. It should be borne in mind that in devices log.0 and log.1 correspond to a voltage of a certain level (or form). The most commonly used are two methods of physical representation of log.0 and log.1: potential and impulse.

In the potential form (Fig. 2.1, a and 2.1, b), a voltage of two levels is used to represent log.0 and log.1: the high level corresponds to log.1 ( level log.1) and the low level corresponds to log.0 ( level log.0). This way of representing the values ​​of logical quantities is called positive logic. It is relatively rare to use the so-called negative logic, in which log.1 is set to a low voltage level, and log.0 to a high level. In what follows, unless otherwise specified, we will use only positive logic.

With a pulse form, log.1 corresponds to the presence of a pulse, and logic 0 corresponds to the absence of a pulse (Fig. 2.1, c).

Note that if in a potential form the information corresponding to the signal (log.1 or log.0) can be determined at almost any time, then in a pulsed form the correspondence between the voltage level and the value of the logical value is established at certain discrete moments in time (the so-called clock moments), indicated in Fig. 2.1, in integers t = 0, 1, 2,...

General designations of logical elements.

Logic gates based on AND, OR, NOT on discrete components.

diode element OR (assembly)

A diode-based OR gate has two or more inputs and one output. The element can operate with both potential and impulse representation of logical quantities.

In Fig. Figure 2.2a shows a diagram of a diode element for working with potentials and pulses of positive polarity. When using negative logic and negative potentials, or pulses of negative polarity, it is necessary to change the polarity of the diodes, as shown in Figure 2.2,b.

Let's consider the operation of the circuit in Fig. 2.2,a. If a pulse (or high potential) acts on only one input, then the diode connected to this input opens and the pulse (or high potential) is transmitted through the open diode to resistor R. In this case, a voltage of the polarity at which the diodes in the circuits is formed on resistor R the remaining inputs are subject to the blocking voltage.

rice. 2.2.

If signals corresponding to logic 1 are simultaneously received at several inputs, then if the levels of these signals are strictly equal, all diodes connected to these inputs will open.

If the resistance of the open diode is small compared to the resistance of resistor R, the output voltage level will be close to the input signal level, regardless of how many inputs the logic 1 signal is simultaneously active on.

Note that if the levels of the input signals differ, then only the diode of the input whose signal level is the highest is opened. A voltage is generated across resistor R that is close to the highest of the voltages acting at the inputs. All other diodes close, disconnecting sources with low signal levels from the output.

Thus, a signal corresponding to logic 1 is generated at the output of the element if logic 1 is active at at least one of the inputs. Therefore, the element implements the disjunction operation (OR operation).

Let's consider the factors influencing the shape of the output pulse. Let the element have n inputs and one of them is supplied with a rectangular voltage pulse from a source with output resistance Rout. The diode connected to this input is open and represents a low resistance. The separate diodes are closed, the capacitances C of their p-n junctions through the output resistances of the sources connected to the inputs turn out to be connected in parallel with the output of the element. Together with the load and installation capacitance C n, some equivalent capacitance C eq = C d + (n-1) C d is formed, connected in parallel R (Fig. 2.3, a).

At the moment a pulse is applied to the input, due to the capacitance Cec, the output voltage cannot increase abruptly; it grows exponentially with time constant

(since R out< R), стремясь к значению U вх R/(R + R вых).

rice. 2.3.

At the moment the input pulse ends, the voltage across the charged capacitor C eq cannot drop abruptly; it decreases exponentially with a time constant (at this time all diodes are closed); because the cutoff duration of the output pulse is longer than the duration of its front (Fig. 2.3, b). Applying the next pulse to the input of the element is allowed only after the residual voltage at the output from the action of the previous pulse decreases to a certain small value. Therefore, a slow drop in output voltage necessitates an increase in the clock interval and, therefore, causes a decrease in performance.

diode element AND (matching circuit)

An AND gate has one output and two or more inputs. The AND diode element can work with information presented in both potential and pulse form.

Figure 2.4a shows the circuit used for positive input voltages. When using negative logic and negative input voltages, or pulses of negative polarity, it is necessary to change the polarity of the power supply voltage and the polarity of the diodes (Fig. 2.4b).

rice. 2.4.

Let one of the inputs of the circuit in Fig. 2.4a have a low voltage level corresponding to the log.0 level. The current will be closed in the circuit from source E through resistor R, an open diode and a low input voltage source. Since the resistance of an open diode is low, a low potential from the input will be transmitted through the open diode to the output. The diodes connected to the remaining inputs, which are exposed to a high voltage level, turn out to be closed. The voltage acting on the diode can be determined by summing the voltages when bypassing the circuit external to the diode from its anode to the cathode. With this bypass, the voltage on the diode is equal to U d = U out - U in. Thus, the output voltage applied to the anodes of the diodes is positive for them, tending to open the diodes; the input voltage applied to the cathode is negative, tending to close the diode. And if u out< u вх, то U д отрицательно и диод закрыт. Именно поэтому, когда на выходе элемента низкий потенциал (уровень лог.0), а на входе высокий потенциал (уровень лог.1), подключенный к этому входу диод оказывается закрытым.

Thus, if at least one of the inputs has a low-level voltage (log.0), then a low-level voltage (log.0) is generated at the output of the element.

Let high-level voltages operate at all inputs (log.1). They may differ slightly in meaning. In this case, the diode that is connected to the input with a lower voltage will be open. This voltage will be transmitted through the diode to the output. The remaining diodes will be practically closed. The output voltage will be set to a high level (log.1).

Consequently, a logic 1 level voltage is set at the output of the element if and only if a logic 1 level voltage operates at all inputs. Thus, we make sure that the element performs the logical AND operation.

Let's consider the shape of the output pulse (Fig. 2.5).

We will assume that some equivalent capacitive element C eq is connected to the output, the capacitance of which includes the capacitances of the load, installation and closed diodes. At the moment a voltage pulse is applied simultaneously to all inputs, the voltage at C eq (at the output of the element) cannot increase abruptly. All diodes initially turn out to be closed by input voltages, which are negative for the diodes. Therefore, input signal sources will be disconnected from C eq. Capacitor C eq is charged from source E through resistor R. The voltage at the capacitor (and therefore at the output of the element) grows exponentially with a time constant (Fig. 2.5b). At the moment when uout exceeds the minimum input voltage, the corresponding diode will open and the growth of uin will stop. The current from source E, previously closed through C eq, is switched into the open diode circuit.

rice. 2.5.

At the moment the input pulses end, all diodes open with a positive voltage uout for them. A relatively fast discharge of C eq occurs through open diodes and low output resistances of input signal sources. The output voltage decreases exponentially with a small time constant.

A comparison of the shapes of the output pulses of the diode elements OR and AND shows that in the OR element the cutoff of the pulse is more extended, and in the AND element its front is more extended.

transistor element NOT (inverter)

rice. 2.6.

The operation cannot be implemented by the key element shown in Fig. 2.6,a. It should be kept in mind that this element performs the NOT operation only on the potential form of representation of logical values. When the input signal level is low, corresponding to log.0, the transistor is closed, and a high level voltage E (log1) is set at its output. And vice versa, at a high input voltage level (log.1 level), the transistor is saturated, and a voltage close to zero is set at its output (log.0 level). Graphs of input and output voltages are presented in Fig. 2.6, b.

Integral logical elements of the AND-NOT basis and their parameters.

Integral logic elements are used in the potential form of representing logical quantities.

The diagram of an integrated element AND-NOT type DTL is shown in Fig. 2.7. An element can be divided into two functional parts connected in series. The input quantities are supplied to the part that is a diode AND gate. The second part of the element, made on a transistor, is an inverter (performing the NOT operation). Thus, the element sequentially performs the logical operations AND and NOT and, therefore, as a whole it implements the logical AND-NOT operation.

If a high-level voltage (log.1) operates at all inputs of the element, then a high-level voltage is generated at the output of the first part of the circuit (at point A). This voltage is transmitted through the VD diodes to the input of the transistor, which is in saturation mode; at the output of the element the voltage is low (log.0).

rice. 2.7.

If at least one of the inputs has a low-level voltage (log.0), then a low-level voltage (close to zero) is formed at point A, the transistor is closed and a high-level voltage (log.1) is at the output of the element. The operation of the diode element AND in the integrated version differs from the operation of the same element discussed above on discrete components in that when logic 1 is simultaneously applied to all inputs, all diodes turn out to be closed. Due to this, the current consumption from the source supplying the input voltage to log.1 is reduced to a very small value.

Let's take a closer look at the operation of the inverter part of the element. First, let's note some features of integrated circuit transistors. The microcircuits use silicon transistors of the n-p-n type (in this case, the collector supply voltage has a positive polarity and the transistor opens when there is a positive voltage between the base and emitter). In Fig. Figure 2.8 shows a typical dependence of the collector current on the voltage between the base and emitter in the active mode. The peculiarity of this characteristic is that practically the transistor begins to open at relatively high values ​​of the base voltage (usually exceeding 0.6 V). This feature allows you to do without sources of base bias, since even at positive voltages at the base of tenths of a volt, the transistor turns out to be practically closed. Finally, another feature of the microcircuit transistor is that the voltage between the collector and emitter in saturation mode is relatively high (it can be 0.4 V or higher).

rice. 2.8.

Let the signals to the inputs of a logical element be supplied from the outputs of similar elements. Let us take the log.1 voltage equal to 2.6 V, the log.0 voltage equal to 0.6 V, the voltage on the open diodes and the base-emitter voltage of the saturated transistor equal to 0.8 V.

When a voltage of 2.6 V (log 1 level) is applied to all inputs (see Fig. 2.7), the diodes at the inputs close, the current from the source E 1 through the resistor R 1, the diodes VD passes into the base of the transistor, setting the transistor to saturation mode . A low level voltage of 0.6 V (log level 0) is generated at the output of the element. The voltage U A is equal to the sum of the voltages on the diodes VD and the voltage U BE: 3 0.8 = 2.4 V. Thus, the input diodes are under a reverse voltage of 0.2 V.

If at least one of the inputs is supplied with a low level voltage of 0.6 V (log level 0), then the current from source E 1 is closed through resistor R 1, an open input diode and the input signal source. In this case, U A = 0.8 + 0.6 = 1.4 V. At this voltage, the transistor turns off due to the bias provided by the VD diodes (these diodes are called bias diodes). The current from the source E 1, flowing through resistor R 1, diodes VD and resistor R 2, creates a voltage drop on the bias diodes close to U A. The voltage U BE is positive, but significantly less than 0.6 V, and the transistor is closed.

AND-NOT element of diode-transistor logic (DTL)

The basic circuit of the element shown in Fig. 2.9, like the circuit of the DTL element discussed above, consists of two functional parts connected in series: a circuit that performs the AND operation, and an inverter circuit. A distinctive feature of the construction of the AND circuit in the TTL element is that it uses one multi-emitter transistor MT, replacing a group of input diodes of the DTL circuit. The emitter junctions of the MT act as input diodes, and the collector junction acts as a bias diode in the transistor base circuit of the inverting part of the element circuit.

When considering the principle of operation of the MT, it can be imagined as consisting of individual transistors with combined bases and collectors, as shown in Fig. 2.9, b.

rice. 2.9

Let a logic 1 level voltage (3.2 V) be applied to all inputs of the element. The possible distribution of potentials at individual points of the circuit is shown in Fig. 2.10a. The emitter junctions MT turn out to be reverse biased (the emitter potentials are higher than the base potentials), the collector junction MT, on the contrary, is biased in the forward direction (the collector potential is lower than the base potential). Thus, MT can be represented by transistors operating in active mode with inverse switching (in such switching, the emitter and collector change roles). The multi-emitter transistor is designed in such a way that its gain in inverse connection is much less than unity. Therefore, emitters select a small current from input signal sources (unlike DTL elements, where this current through closed input diodes is practically zero). The base current MT flows through the collector junction into the base of the transistor VT, keeping the latter in saturation mode. The output voltage is set to a low level (log.0).

rice. 2.10.

Let's consider another state of the circuit. Let at least one of the inputs have a voltage level of log.0. The resulting potential distribution is shown in Fig. 2.10b. The MT base potential is higher than the emitter and collector potential. Consequently, both junctions, emitter and collector, are forward biased and the MT is in saturation mode. The entire base current of the MT is closed through the emitter junctions. The voltage between the emitter and the collector is close to zero, and the low voltage level acting on the emitter is transmitted through the MT to the base of the transistor VT. Transistor VT is closed, the output voltage level is high (log level 1). In this case, almost the entire base current of the MT is closed through the forward-biased emitter junction of the MT.

Basic parameters of integrated logic elements

Let's look at the main parameters and ways to improve them.

Input pooling factor determines the number of element inputs intended to supply logical variables. An element with a large input combining coefficient has wider logical capabilities.

Load capacity (or output fanout ratio) determines the number of inputs of similar elements that can be connected to the output of a given element. The higher the load capacity of the elements, the fewer the number of elements may be required when building a digital device.

To increase the load capacity in DTL and TTL, a complicated circuit of the inverting part is used. The diagram of an element with one of the variants of a complex inverter is shown in Fig. 2.11.

rice. 2.11

Figure 2.11a illustrates the enabled element mode. If all inputs have a logic level voltage of 1, all current flowing through resistor R1 is supplied to the base of transistor VT2. Transistor VT2 opens and goes into saturation mode. The emitter current of transistor VT2 flows into the base of transistor VT5, keeping this transistor open. Transistors VT3 and VT4 are closed, since at the emitter junction of each of them a voltage of 0.3 V is applied, which is insufficient to open the transistors.

In Fig. 2.11b shows the mode of the element being turned off. If at least one of the inputs has a voltage level of log.0, then the current of resistor R1 is completely switched to the input circuit. Transistors VT2 and VT5 close, the output voltage is at log.1 level. Transistors VT3, VT4 operate in two series-connected emitter followers, the input of which is supplied with current through resistor R2, and the emitter current of transient VT4 powers the load.

When the element with a simple inverter is turned off, current is supplied to the load from the power source through a collector resistor Rк with a high resistance (see Fig. 2.11b). This resistor limits the maximum current value in the load (as the load current increases, the voltage drop across Rk increases, the output voltage decreases). In an element with a complex inverter, the emitter current of transistor VT4, operating in an emitter follower circuit, is supplied to the load. Since the output resistance of the emitter follower is small, the output voltage is less dependent on the load current and large values ​​of the load current are permissible.

Performancelogical elements is one of the most important parameters of logical elements; it is estimated by the delay in signal propagation from the input to the output of the element.

Figure 2.12 shows the shape of the input and output signals of the logical element (inverter): t 1.0 3 - delay time for switching the element output from state 1 to state 0; t 0.1 3 - switching delay from state 0 to state 1. As can be seen from the figure, the delay time is measured at a level averaged between the log.0 and log.1 levels. The average signal propagation delay t з av = 0.5 (t 0.1 3 + t 1.0 3). This parameter is used in calculating the propagation delay of signals in complex logic circuits.

rice. 2.12

Let's consider the factors influencing the performance of a logical element and methods for increasing performance.

To increase the switching speed of transistors in the element, it is necessary to use higher-frequency transistors and switch the transistors with large control currents in the base circuit; a significant reduction in the delay time is achieved through the use of a saturated mode of operation of transistors (in this case, the time required for the resorption of minority carriers in the base when the transistors are turned off) is eliminated.

rice. 2.13

This process can be accelerated by the following methods:

· a decrease in R (and therefore a decrease in the time constant); however, at the same time, the current and power consumed from the power source increase;

· use of small voltage drops in the element;

· the use of an emitter follower element at the output, which reduces the influence of load capacitance.

Below, when describing the logical elements of emitter-coupled logic, the use of these methods to increase the speed of the elements is shown.

rice. 2.13

Noise immunity is determined by the maximum value of interference that does not cause disruption to the operation of the element.

To quantitatively assess noise immunity, we will use the so-called transfer characteristic logical element (inverter). Figure 2.14 shows a typical form of this characteristic.

rice. 2.14

The transfer characteristic is the dependence of the output voltage on the input. To obtain it, it is necessary to connect all the inputs of the logic element and, by changing the output voltage, mark the corresponding output voltage values.

As the input voltage increases from zero to the threshold level log.0 U 0 p, the output voltage decreases from the level log.1 U 1 min. A further increase in the input leads to a sharp decrease in the output. At large input voltage values ​​exceeding the threshold level log.1 U 0 max. Thus, during normal operation of the element in static (steady) mode, input voltages U 0 p are unacceptable< u вх

Acceptable noise is considered to be those which, when superimposed on the input voltage, will not bring it into the region of unacceptable values ​​U 0 p< u вх

Emitter-coupled logic gate

A typical circuit of an integrated element of emitter-coupled logic is shown in Fig. 2.15.

rice. 2.15.

Transistors VT 0, VT 1, VT 2, VT 3 operate in the current switch circuit, transistors VT 4, VT 5 - in the output emitter followers. The diagram shows the potential values ​​at various points when a voltage level of log.1 is applied to the input; The values ​​of the potentials of the same points are enclosed in brackets for the case when a voltage level of log.0 is applied to all inputs of the element. The values ​​of these potentials correspond to the following levels:

· power supply voltage Ek = 5 V;

· logic level 1 U 1 = 4.3 V;

· logic level 1 U 0 = 3.5 V;

· the voltage between the base and emitter of the open transistor U be = 0.7 V.

Let's consider the principle of operation of the integrated logical element ESL (see Fig. 2.15).

Let voltage U 1 = 4.3 V be applied to In 1. Transistor VT 1 is open; the emitter current of this transistor creates a voltage drop across resistor R U a = U 1 -U be = 4.3 - 0.7 = 3.6 V; the collector current creates a voltage U Rк1 = 0.8 V on resistor Rk1; voltage at the collector of the transistor U b = E k - U Rk1 = 5 - 0.8 = 4.2 V.

Voltage between the base and emitter of the transistor VT 0 U be VT0 = U - U a = 3.9 - 3.6 = 0.3 V; this voltage is not enough to open the transistor VT 0. Thus, the open state of any of the transistors VT 1, VT 2, VT 3 leads to the closed state of the transistor VT 0. The current through the resistor R k2 is very small (only the base current of the transistor VT 5 flows) and the voltage at the collector VT 0.

Let's consider another state of the logical element. Let a voltage of log.0 U 0 = 3.5 V act at all inputs. In this case, the transistor VT 0 turns out to be open (of all the transistors whose emitters are combined, the one with the higher voltage is opened); U a = U - U be = 3.9 - 0.7 = 3.2 V; the voltage between the base and emitter of transistors VT 1, VT 2, VT 3 is equal to U be VT1...VT0 = U 0 - U a = 3.5 - 0.7 = 0.3 V and these transistors are closed; U b = 5 V; U in = 4.2 V.

Voltages from points b and c are transmitted to the outputs of the element through emitter repeaters; in this case, the voltage level decreases by the value U be = 0.7 V. Let us pay attention to the important fact that the voltages at the outputs are equal to U 1 (4.3 V) or U 0 (3.5 V).

Let's find out what logical function is formed at the outputs of the element.

At point at and at Out 2, a low level voltage is generated when transistor VT 0 is open, i.e. in the case where x 1 = 0, x 2 = 0, x 3 = 0. For any other combination of input variable values, transistor VT 0 is closed and a high level voltage is generated at Out 2. It follows from this that a disjunction of variables x 1 Vx 1 Vx 1 is formed at Out 2. The OR-NOT function is formed at Out 1.

Therefore, the logic gate performs NOR and OR operations.

In ESL microcircuits, point g is made common, and point d is connected to a power source with a voltage of -5V. In this case, the potentials of all points of the circuit are reduced to 5 V.

The considered logical element belongs to the class of the fastest-acting elements (short signal propagation delay time) is ensured by the following factors: open transistors are in active mode (not in saturation mode); the use of emitter followers at the outputs speeds up the process of recharging the capacitors connected to the outputs; transistors are connected according to a common base switching circuit, which improves the frequency properties of transistors and speeds up the process of switching them; The difference in logical levels U 1 -U 0 = 0.8 V was chosen to be small (however, this leads to a relatively low noise immunity of the element).

Logic elements based on MOS transistors

rice. 2.16

In Fig. Figure 2.16 shows a diagram of a logic element with an induced channel of type n (the so-called n MIS technology). The main transistors VT 1 and VT 2 are connected in series, transistor VT 3 acts as a load. In the case when a high voltage U 1 is applied at both inputs of the element (x 1 = 1, x 2 = 1), both transistors VT 1 and VT 2 are open and a low voltage U 0 is set at the output. In all other cases, at least one of the transistors VT 1 or VT 2 is closed and the voltage U 1 is set at the output. Thus, the element performs the logical AND-NOT function.

rice. 2.17

In Fig. Figure 2.17 shows a diagram of the OR-NOT element. A low voltage U 0 is set at its output if at least one of the inputs has a high voltage U 1 , opening one of the main transistors VT 1 and VT 2 .

rice. 2.18

Shown in Fig. 2.18 diagram is a diagram of the NOR-NOT element of the KMDP technology. In it, transistors VT 1 and VT 2 are the main ones, transistors VT 3 and VT 4 are the load ones. Let high voltage U 1. In this case, transistor VT 2 is open, transistor VT 4 is closed and, regardless of the voltage level at the other input and the state of the remaining transistors, a low voltage U 0 is set at the output. The element implements the logical OR-NOT operation.

The CMPD circuit is characterized by very low current consumption (and therefore power) from power supplies.

Logic elements of integral injection logic

rice. 2.19

In Fig. Figure 2.19 shows the topology of the logical element of the integral injection logic (I 2 L). To create such a structure, two phases of diffusion in silicon with n-type conductivity are required: during the first phase, regions p 1 and p 2 are formed, and during the second phase, regions n 2 are formed.

The element has the structure p 1 -n 1 -p 2 -n 1 . It is convenient to consider such a four-layer structure by imagining it as a connection of two conventional three-layer transistor structures:

p 1 - n 1 - p 2 n 1 - p 2 - n 1

The diagram corresponding to this representation is shown in Fig. 2.20, a. Let's consider the operation of the element according to this scheme.

rice. 2.20

Transistor VT 2 with a structure of type n 1 -p 2 -n 1 performs the functions of an inverter with several outputs (each collector forms a separate output of an element according to an open collector circuit).

Transistor VT 2, called injector, has a structure like p 1 -n 1 -p 2 . Since the area n 1 of these transistors is common, the emitter of transistor VT 2 must be connected to the base of transistor VT 1; the presence of a common area p 2 leads to the need to connect the base of transistor VT 2 with the collector of transistor VT 1. This creates a connection between transistors VT 1 and VT 2, shown in Fig. 2.20a.

Since the emitter of transistor VT 1 has a positive potential and the base is at zero potential, the emitter junction is forward biased and the transistor is open.

The collector current of this transistor can be closed either through transistor VT 3 (inverter of the previous element) or through the emitter junction of transistor VT 2.

If the previous logical element is in the open state (transistor VT 3 is open), then at the input of this element there is a low voltage level, which, acting on the basis of VT 2, keeps this transistor in the closed state. The injector current VT 1 is closed through the transistor VT 3. When the previous logic element is closed (transistor VT 3 is closed), the collector current of the injector VT 1 flows into the base of the transistor VT 2, and this transistor is set to the open state.

Thus, when VT 3 is closed, transistor VT 2 is open and, conversely, when VT 3 is open, transistor VT 2 is closed. The open state of the element corresponds to the log.0 state, and the closed state corresponds to the log.1 state.

The injector is a source of direct current (which can be common to a group of elements). Often they use the conventional graphic designation of an element, presented in Fig. 2.21, b.

In Fig. Figure 2.21a shows a circuit that implements the OR-NOT operation. The connection of element collectors corresponds to the operation of the so-called installation I. Indeed, it is enough that at least one of the elements is in the open state (log.0 state), then the injector current of the next element will be closed through the open inverter and a low log.0 level will be established at the combined output of the elements. Consequently, at this output a value is formed corresponding to the logical expression x 1 · x 2. Applying the de Morgan transformation to it leads to the expression x 1 · x 2 = . Therefore, this connection of elements really implements the OR-NOT operation.

rice. 2.21

Logic elements AND 2 L have the following advantages:

· provide a high degree of integration; in the manufacture of I 2 L circuits, the same technological processes are used as in the production of integrated circuits on bipolar transistors, but the number of technological operations and the necessary photomasks is smaller;

· a reduced voltage is used (about 1V);

· provide the ability to exchange power over a wide range of performance (power consumption can be changed by several orders of magnitude, which will correspondingly lead to a change in performance);

· are in good agreement with TTL elements.

In Fig. Figure 2.21b shows a diagram of the transition from the I 2 L elements to the TTL element.

- Input aggregation coefficient K about- the number of inputs with which the logical function is implemented.

- Output fanout factor K times shows how many logical inputs of devices of the same series can be simultaneously connected to the output of a given logical element.

- Performance characterized by the delay time of signal propagation through the LE and is determined from graphs of input and output signals versus time (Figure 10). There is a difference in signal propagation delay time when the LE is turned on t 1,0 z.r., signal delay time when turned off t 0,1 z.r. and average propagation delay time t 1,0 z.r. wed..

Figure 10 To determine the propagation delay time of the LE signal

The average signal propagation delay time is a time interval equal to half the sum of the signal propagation delay times when the logic element is turned on and off:

t health wed= (t 1,0 z.r.+ t 0,1 z.r.)/2

- High U voltage 1 and low U 0 levels(input U 1 input and weekends U 0 out) and their permissible instability. Under U 1 and U 0 understand the nominal voltage values ​​“Log.1” and “Log.0”; instability is expressed in relative units or as a percentage.

- Threshold voltages high U 1 pores and low U 0 pore levels. Threshold voltage is understood to be the smallest ( U 1 since then) or greatest ( U 0 since then) the value of the corresponding levels at which the transition of the logical element to another state begins. These parameters are determined taking into account the spread of parameters of the corresponding series in the operating temperature range; reference books often give one average value U POR.

- Input currents I 0 in, I 1 input respectively at input voltages of low and high levels.

- Noise immunity. Static noise immunity is assessed based on the transfer characteristics of the logic element as the minimum difference between the values ​​of the output and input signals relative to the threshold value, taking into account the spread of parameters in the operating temperature range:

U- POM = U 1 out.min – U POR

U+ POM = U POR – U 0 out.min

The reference data usually provides one permissible interference value, which does not switch the LE under acceptable operating conditions.

- Power consumption P sweat or current consumption I sweat.

- Switching energy- work spent on performing a single switch. This is an integral parameter used to compare microcircuits of different series and technologies. It is found as the product of power consumption and the average signal propagation delay time.

3.2 Transistor-transistor logic

Transistor-transistor logic (TTL) elements form the basis of medium and high-speed microcircuits. Several variants of schemes with different parameters have been developed and are used.

Figure 11 NAND logic elements with a simple a) and complex b) inverter

3.2.1 TTL NAND element with a simple inverter

Such an element includes a multi-emitter transistor VT1 (Figure 11,a), which performs the logical AND operation, and a transistor VT2, which implements the NOT operation.

The multi-emitter transistor (MET) is the basis of TTL. If there is a circuit at the inputs, i.e. MET signal emitters U 0 =U CE.us The emitter junctions are forward biased and a significant base current flows through VT1 I B 1 =(E–U BE.us –U CE.us)/R B, sufficient for the transistor to be in saturation mode. In this case, the collector-emitter voltage VT 1 U CE.us=0.2 V. The voltage at the base of transistor VT2 is equal to U 0 +U CE.us=2U CE.us<U BE.us and transistor VT2 is closed. The voltage at the output of the circuit corresponds to the logical level “1”. The circuit will be in this state as long as the signal at at least one of the inputs is equal to U 0 .

If the input voltage is increased from the level U 0 on all inputs simultaneously, or on one of the inputs, provided that a logical “1” signal is applied to the remaining inputs, then the input voltage at the base increases and when U b=U in+U CE.us=U BE.us and transistor VT2 will open. As a result, the base current VT2 will increase, which will flow from the power source through the resistor R b both the collector junction VT1 and the transistor VT2 will go into saturation mode. Further increase U VX will lead to the blocking of the emitter junctions of transistor VT1, and as a result it will go into a mode in which the collector junction is biased in the forward direction, and the emitter junctions are biased in the opposite direction (Inverse switching mode). Circuit output voltage U OUT=U CE.us=U 0 (transistor VT2 in saturation).

Thus, the considered element performs the logical AND-NOT operation.

The simplest circuit of a TTL element has a number of disadvantages. When such elements are connected in series, when the emitters of other similar elements are connected to the output of the element, the current consumed from the LE increases, and the high-level voltage decreases (log. “1”). Therefore, the element has a low load capacity. This is due to the presence of large emitter currents of the multi-emitter transistor in inverse mode, which are consumed from the LE by load transistors.

In addition, this circuit has low noise immunity with respect to the level of positive interference: U+ POM = U BE.us –U 0 =U BE.us–2U CE.us. To eliminate these shortcomings, TTL circuits with a complex inverter are used (Figure 11,b).

3.2.2 TTL element with complex inverter

A TTL circuit with a complex inverter (Figure 11, b), just like a circuit with a simple inverter, carries out a logical AND-NOT operation. If there is voltage at the inputs, log. “0” multi-emitter transistor VT1 is in saturation mode, and transistor VT2 is closed. Consequently, transistor VT4 is also closed, since current does not flow through resistor R4 and voltage at the base of VT4 U bae 4 = "0". Transistor VT3 is open since its base is connected to power source E through resistor R2. The resistance of resistor R3 is small, so VT3 works as an emitter follower. The load current of the logic element and the output voltage corresponding to the log level flow through transistor VT3 and the open diode VD. “1” is equal to the supply voltage minus the voltage drop U BE.us, voltage drop across an open diode U d=U BE.us and a small voltage drop across resistance R 2 from the base current VT2: U¹= E–2U CE.us– R 2 I B 2 = U n– 2U BE.us.

The considered mode corresponds to section 1 of the transfer characteristic of the TTL logic element (Figure 12.a)

Figure 12 Characteristics of the basic LE series 155:

a – transmission, b – input.

As the voltage at all inputs increases, the potential of the VT2 base increases and when U VX=U 0 since then transistor VT2 opens, collector current begins to flow I K 2 through resistors R2 and R4. As a result, the base current of VT3 decreases, the voltage drop across it increases and the output voltage decreases (section 2 in Figure 12). While there is a voltage drop across resistor R4 U R 4 <U BE.us transistor VT4 is closed. When U VX=U¹ since then =2U BE.us–U CE.us transistor VT4 opens. A further increase in the input voltage leads to saturation of VT2 and VT4 and the transition of VT1 to inverse mode (section 3 in Figure 12). In this case, the potential of the point " A"(see Figure 11, b) is equal to Ua=U BE.us+U CE.us, and the points " b» - U b=U CE.us, hence, U ab=U a–U b=U BE.us. To unlock transistor VT3 and diode VD1, you need U ab≥2U BE.us. Since this condition is not met, VT3 and VD1 are closed and the voltage at the circuit input is equal to U CE.us=U 0 (section 4 in Figure 12).

When switching, there are periods of time when both transistors VT3 and VT4 are open and current surges occur. To limit the amplitude of this current, a resistor with a small resistance (R 3 = 100–160 Ohms) is included in the circuit.

At a negative voltage on the MET emitters greater than 2 V, a tunnel breakdown develops and the input current increases sharply. To protect the LE from the effects of negative interference, diodes VD2, VD3 are introduced into the circuit, which limit it at the level of 0.5–0.6V.

With a positive voltage greater than (4–4.5) V, the input current also increases, therefore, to supply the LE inputs with a log. “1” the inputs cannot be connected to the +5 V supply voltage.

In the practical application of LE TTL, unused inputs can be left free. However, this reduces noise immunity due to the effect of interference on free terminals. Therefore, they are usually either combined with each other, if this does not lead to an excess for the previous LE, or connected to a +5 V power source through a resistor R = 1 kOhm, which limits the input current. Up to 20 inputs can be connected to each resistor. With this method the level is log. "1" is created artificially.

Noise immunity of a TTL element with a complex inverter:

U + pom = U 1 since then – U 0 = 2U BE.us – 2U CE.us

U – pom = U 1 – U 1 since then = E – 4U BE.us + U CE.us

The performance of TTL elements, determined by the signal propagation delay time when turned on t 1,0 ass.r and turning off t 0,1 ass.r, depends on the duration of the processes of accumulation and resorption of minority carriers in the bases of transistors, recharging the capacitances of collector SCs and emitter capacitors of SC junctions. Since during operation of the TTL element the open transistors are in a state of saturation, a significant contribution to the increase in the inertia of the TTL is made by the time of resorption of minority carriers when the transistors are turned off.

TTL elements with a complex inverter have a large logic swing, low power consumption, high performance and noise immunity. Typical TTL parameter values ​​are as follows: U pit=5 V; U 1 ≥2.8 V; U 0 ≤0.5 V; t building=10...20 ns; P pot.sr.=10...20 mW; K times=10.

In the practical application of LE TTL, unused inputs can be left free. However, this reduces noise immunity due to the effect of interference on free terminals. Therefore, they are usually either combined with each other, if this does not lead to an excess for the previous LE, or connected to a +5 V power source through a resistor R = 1 kOhm, which limits the input current. Up to 20 inputs can be connected to each resistor.

3.2.3 TTLSH elements

In order to increase the performance of TTL elements, TTLSH elements use Schottky transistors, which are a combination of a conventional transistor and a Schottky diode connected between the base and collector of the transistor. Since the on-state voltage drop across a Schottky diode is less than that of a conventional pn junction, most of the input current flows through the diode and only a small fraction flows into the base. Therefore, the transistor does not enter deep saturation mode.

Consequently, the accumulation of carriers in the base due to their injection through the collector junction practically does not occur. In this regard, there is an increase in the speed of the transistor switch with a Schottky barrier as a result of a decrease in the rise time of the collector current when turned on and the resorption time when turned off.

The average signal propagation delay time of TTL elements with Schottky diodes (TTLS) is approximately two times less compared to similar TTL elements. The disadvantage of TTLSh is lower noise immunity compared to similar TTL elements. U + pom due to higher value U 0 or less U por.

3.2.4 TTL elements with three output states -

have an additional input V - permission input (Figure 13, a). When voltage is applied to this input U 0 transistor VT5 is open and saturated, and transistors VT6 and VT7 are closed and therefore do not affect the operation of the logic element. Depending on the combination of signals at the information inputs, the output of the LE may be a signal with a “log” level. 0" or "log. 1". When a voltage is applied to the V input with a level of “log. 1" transistor VT5 closes, and transistors VT6 and VT7 open, the voltage at the base of transistor VT3 decreases to the level U BE.us+U d, transistors VT2, VT3, VT4 close and the LE goes into a high-impedance (third) state, that is, it is disconnected from the load.

Figure 13b shows the UGO of this element. The ∇ symbol indicates that the output has three states. Icon E∇ “Resolution of the third state” indicates that with the =0 signal the LE is transferred to the third (high-resistance) state.

To reduce interference along the power supply circuit, decoupling ceramic capacitors with a capacity of about 0.1 μF per case are installed at the connection points to the buses of LE groups. On each board, between the power circuit and the common bus, there are 1–2 electrolytic capacitors with a capacity of 4.7–10 μF.

Figure 13 TTL AND-NOT logical element with three output states a) and its UGO b).

Table 7 shows the parameters of some series of LE TTL.

Table 7 Parameters of some series of TTL logic elements

OPTIONS	SERIES
	Universal	High performance		Micropower
	133, 155	K531	KR1531	K555	Kr1533
Input current I 0 VX, mA	-1,6	-2,0	-0,6	-0,36	-0,2
Input current I 1 VX, mA	0,04	0,05	0,02	0,02	0,02
Output voltage U 0 EXIT, IN	0,4	0,5	0,5	0,5	0,4
Output voltage U 1 EXIT, IN	2,4	2,7	2,7	2,7	2,5
Output fanout ratio K TIMES	10	10	10	20	20
Input pooling factor K ABOUT	8	10	-	20	-
Signal propagation delay time t REAR	19	4,8	3,8	20	20
Current consumption, mA:
I 0 SWEAT(at U 0 EXIT)	22	36	10,2	4,4	3
I 1 SWEAT(at U 1 EXIT)	8	16	2,8	1,6	0,85
	0,4	0,3	0,3	0,3	0,4
Supply voltage, V	5	5	5	5	5
Output currents, mA:
I 0 EXIT	16	20	20	8	4
I 1 EXIT	-0,4	-1	-1	-0,4	-0,4
Average power consumption per element, mW	10	19	4	2	1,2

3.3 Emitter-coupled logic

The basis of emitter-coupled logic (ECL) is a high-speed current switch (Figure 14a). It consists of two transistors, in the collector circuit of which load resistors RK are included, and in the emitter circuit of both transistors there is a common resistor Re, significantly larger in value than Rk. The input signal Uin is supplied to the input of one of the transistors, and the reference voltage Uop is supplied to the input of the other. The circuit is symmetrical, therefore, in the initial state (U in = U op) the same currents flow through both transistors. The total current I O flows through the resistance Re.

Figure 14 Emitter-coupled logic: a) current switch;

b) simplified circuit diagram

When increasing U in the current through transistor VT1 increases, the voltage drop across the resistance R e increases, transistor VT2 closes and the current through it decreases. With an input voltage equal to the level log “1” ( Uin =U 1), transistor VT2 closes and all current flows through transistor VT1. Circuit parameters and current I 0 are selected in such a way that transistor VT1, when open, operates in linear mode at the border of the saturation region.

When decreasing U in to log level "0" ( U in=U 0), on the contrary, transistor VT1 is closed, and transistor VT2 is in linear mode on the border with the saturation region.

In the ESL circuit (Figure 14b), one or more transistors (depending on the input coupling coefficient) are connected in parallel to transistor VT1, which make up one of the arms of the current switch. To increase the load capacity, two emitter followers VT4 and VT5 are connected to the LE outputs.

When applying a signal to all inputs or to one of them, for example, the first U VX 1 =U 1, transistor VT1 opens and current I 0 flows through it, and transistor VT3 closes.

U OUT 1 = U 1 – U BE.us = U 0

U OUT 2 = U PIT – U BE.us = U 1

Thus, with respect to the first output, this circuit implements the logical OR-NOT operation, and with respect to the second output, the OR operation. It is easy to see that the threshold voltage U POR =U OP, logic edge Δ U=U 1 -U 0 =U BE.us and noise immunity of the circuit U + POM=U - POM=0,5U BE.us.

The input currents of the element, and therefore the load currents of the ESL, are small: I 0 VX≈0, current I 1 VX equal to the base current of the transistor operating at the edge of the saturation region, and not in the saturation region. Therefore, the load capacity of the element is high and the branching coefficient reaches 20 or more.

Since the logical difference is small, the instability of the power supply voltage significantly affects the noise immunity of the ESL. To increase noise immunity in ESL circuits, the positive pole of the power source is not grounded, but the positive one. This is done so that a large portion of the interference voltage drops at a high resistance R e and only a small fraction of it reaches the inputs of the circuit.

When using LE ESL and TTL together, it is necessary to include special microcircuits between them that coordinate the levels of logical signals. They are called level converters(PU).

The high performance of ESL is due to the following main factors:

1 Open transistors are not in saturation, so the stage of resorption of minority carriers in the bases is excluded.

2 The input transistors are controlled from the emitter followers of the preceding elements, which, having a low output resistance, provide a large base current and, therefore, a short opening and closing time of the input and reference transistors.

All these factors together ensure short rise and fall times of the output voltage of ESL elements.

The following average parameters are typical for ESL: U pit=–5V; U 1 =–(0.7–0.9)V; U 0 =–(1.5–2)V; tZ D.av=3–7 ns; P sweat=10–20 mW.

The K500 and K1500 series are considered promising, with the K1500 series being subnanosecond and having a propagation delay time of less than 1 ns. (Table 8).

Table 8 Parameters of the main series of LE ESL

Options	Series
	K500	K1500
Input current I 0 VX,mA	0,265	0,35
Input current I 1 VX, mA	0,0005	0,0005
Output voltage U 0 EXIT, IN	-1,85…-1,65	-1,81…-1,62
Output voltage U 1 EXIT, IN	-0,96…-0,81	-1,025…-0,88
Output threshold voltage, V:
U 0 OUTPUT	-1,63	-1,61
U 1 OUTPUT	-0,98	-1,035
Propagation delay time, ns	2,9	1,5
Permissible interference voltage, V	0,125	0,125
Fanout factor K TIMES	15	-
Supply voltage, V	-5,2; -2,0	-4,5; -2,0
Power consumption per element, mW	8…25	40

3.4 Directly coupled transistor logic (DLC)

In the circuit of the TLNS element, the load resistance is included in the circuit of connected collectors of two transistors (Figure 15,a). The input signals X1 and X2 are fed to the bases of these transistors. If X1 and X2 are simultaneously equal to “log 0”, then both transistors are closed and the output of the circuit will have a high potential Y = 1. If a high potential “log 1” is applied to at least one or both inputs, then one or both transistors are open and the output of the circuit will have a low potential Y = 0. Thus, the circuit performs an OR-NOT operation.

Figure 15 LE NSTL a) and input characteristics of load transistors b).

As you can see, the NSTL element circuit is extremely simple, but it has a significant drawback. When the output of the element is set to a log potential. “1”, a constant potential is applied to the bases of the load transistors, as shown in Figure 15, a dotted line U¹. Due to the scatter in the parameters of the transistors (see Figure 15, b), the base currents of the transistors can vary significantly. As a result, one of the transistors may enter deep saturation, while the other may be in linear mode. In this case, the “log.1” levels will differ significantly, which will invariably lead to malfunctions in the operation of the device as a whole. Therefore, the LE NSTL circuit is used only with voltage-controlled transistors.

3.5 Integral injection logic

Elements of integrated injection logic (I²L) have no analogues in discrete circuitry and can only be implemented in an integrated version (Figure 16, a). The I²L element consists of two transistors: a horizontal pnp transistor acts as an injector, and a vertical multicollector npn transistor operates in inverter mode. The common n-type region serves as the base of the pnp transistor as well as the emitter of the npn transistor and is connected to the “ground” point. The collector of the pnp transistor and the base of the npn transistor are also a common area. An equivalent circuit is shown in Figure 16b.

Figure 16 Transistor with injection power: a - block diagram, b - equivalent circuit, c - equivalent circuit with a current generator.

Supply voltage is supplied to the injector emitter-base circuit U PIT. The minimum source voltage is determined by the voltage drop across the emitter junction: U CE.us=0.7 V. But to stabilize the emitter current I 0 resistor R is connected in series with the source and the voltage of the power source is taken U PIT=1...1.2 V. In this case, the p-n junction emitter-base VT1 is open and diffusion of holes to the collector junction takes place. As they move towards the collector, some of the holes recombine with electrons, but a significant part of them reaches the collector junction and, having passed through it, enters the p-base of the inverter (transistor VT2). This process of diffusion, i.e. holes are constantly injected into the base, regardless of the input influence.

If the voltage at the base of VT2 U in=U 0, which corresponds to the closed state of the switch S, holes entering the p-base of the inverter flow freely to the negative pole of the power source. No current flows in the collector circuit of transistor VT2 and this is equivalent to the open state of the collector circuit VT2. This state of the output circuit corresponds to the log voltage. "1".

At U in=U 1 (switch S is open) holes accumulate in the p-base of the inverter. The base potential begins to increase and, accordingly, the voltages at the VT2 transitions decrease until these transitions open. Then a current will flow in the collector circuit of transistor VT2 and the potential difference between the emitter and collector of the inverter (transistor VT2) will be close to zero, i.e. this transistor represents a short-circuited section of the circuit, and this state will correspond to the log level. "0". Thus, the considered element acts as a key.

As is known, the collector current of a transistor connected to a circuit with a common base does not depend on changes in the voltage on the collector over a wide range. Transistor VT1 is included in the circuit with OB. From the theory of operation of a bipolar transistor it is known that its output characteristic, taken at a constant emitter current, is almost horizontal, that is, the collector current does not depend on the voltage on the collector. Therefore, it can be replaced by an equivalent current generator. According to the equivalent current generator theorem, adding or subtracting DC voltage from a current source does not affect the current value of that generator. In accordance with this, the transistor circuit with injection power appears to be a simpler equivalent circuit shown in Figure 16c.

If U in=U 1 , then the current I 0 from the current generator flows into the base of VT2, opening it. Wherein U in=U 0 . If U in=U 0, then current I 0 is shorted to ground, transistor VT2 is closed and U out=U 1 .

Figure 17 Integrated injection logic (I²L): circuit of the OR-NOT element a) and implementation of the logical function AND b).

The use of a multi-collector transistor makes it possible to divide the total collector current VT2 into several identical portions, sufficient to control the input of one similar element. Thanks to this, it becomes possible to use the simplest circuit of a logical element OR-NOT, shown in Figure 17, a. This circuit is similar to the circuit of the NSTL element (see Figure 15, a). Unlike the circuit of the NOR-NOT NSTL element, the NOR-NOT AND²L element does not even require a resistor in the combined collector circuit, since the collector circuit receives power from the current generator of the subsequent stage.

Figure 17b shows a circuit that implements the logical function AND. When a logic signal is applied to both inputs (X1 and X2). “0” on the combined collectors of the inverters (VT3 and VT4) will be a log level. "1". When a log signal is applied to one of the inputs, or to both inputs simultaneously. “1”, at the output of the circuit we have a log signal. “0”, which corresponds to the execution of a logical AND operation.

I²L elements occupy a small area on the substrate and have low power consumption and switching energy. They are characterized by the following parameters: U PIT=1 V; t set.=10...100 ns; K times=3,5; K rev=1.

3.6 Logic elements based on MOS transistors

MOS transistor logic elements use two types of transistors: control and load. Controllers have a short but fairly wide channel and therefore have a high transconductance value and are controlled by low voltage. Load ones, on the contrary, have a longer but narrow channel, therefore they have a higher output resistance and act as a large active resistance.

3.6.1 Logic elements on keys with dynamic load

Logic elements on switches with dynamic loads consist of one load and several control transistors. If the control transistors are connected in parallel, then, as in NSTL (see Figure 15, a), the element performs a logical OR-NOT operation, and when connected in series, it performs an AND-NOT operation (Figure 18, a, b).

Figure 18 Diagrams of MOS TL elements: a) – OR-NOT, b) – AND-NOT.

If there is voltage at inputs X1 and X2 U ВХ =U 0 <U ZI.por control transistors VT1 and VT2 are closed. In this case, the output voltage corresponds to the log level. "1". When voltage is applied to one or both inputs of an element U ВХ =U 1 >U ZI.por, then at the output we have a log. “0”, which corresponds to the execution of a logical OR-NOT operation.

In the AND-NOT element circuit, the control transistors are connected in series, so the level is log. “0” at the output of the circuit occurs only when there are single signals at both inputs.

MOS TL elements have high noise immunity, a large logical difference, low power consumption and relatively low performance. For elements based on low-threshold MOS transistors, it is usually U PIT=5...9 V, and at high threshold U PIT=12.6…27 V. Main parameters of MOS TL: P sweat=0.4...5 mW, t ZD.av=20...200 ns; U 0 ≤1 V; U 1 ≈7 V.

3.6.2 Logical elements on complementary keys

The complementary switch consists of two MOS transistors with channels of different conductivity types, the inputs of which are connected in parallel and the outputs in series (Figure 19a). When the gate voltage is greater than the threshold, for a transistor with a channel of a certain type, the corresponding transistor is open and the other is closed. When the voltage is of opposite polarity, the open and closed transistors change places.

LEs on complementary switches (CMOS) have a number of undeniable advantages.

They operate successfully when the power source voltage varies over a wide range (from 3 to 15 V), which is unattainable for LEs that include resistors.

In static mode with high load resistance, CMOS LEs consume virtually no power.

They are also characterized by: stability of output signal levels and its small difference from the power source voltage; high input and low output resistance; ease of coordination with microcircuits of other technologies.

Figure 19 Circuits of CMOS TL logic elements: a) inverter, b) NOR, c) NAND.

The circuit of a CMOS LE performing the 2OR-NOT function is shown in Figure 19b. Transistors VT1 and VT3 have a p-type channel and are open at gate voltages close to zero. Transistors VT2 and VT4 have an n-type channel and are open at gate voltages greater than the threshold value. If both or one of the inputs has a log level. “1”, then the output of the circuit will be a log signal. “0”, which corresponds to the execution of a logical OR-NOT operation.

If groups of tiered and parallel-connected transistors are swapped, then an element will be implemented that performs the AND-NOT function (Figure 19c). It works similar to the previous one. Transistors VT1 and VT3 have a p-type channel and are open when the gate voltage is close to zero. Transistors VT2 and VT4 have an n-type channel and are open at gate voltages greater than the threshold value. If both of these transistors are open, then the “log” signal will be set at the output. 0".

Thus, the combination of parallel connection of transistors with p-type channels of electrical conductivity, and tiered connection of transistors with n-type channels made it possible to implement the AND-NOT function.

In LE CMOS, elements with three stable states are very simply implemented. To do this, two complementary transistors VT1, VT4 (Figure 20a), controlled by inverse signals, are connected in series with the inverter transistors

Figure 20 Inverter with three output states a); coordination of TTL LE with CMOS LE b).

Matching TTL LE with CMOS LE can be done in several ways:

1) Power the CMOS LE with low voltage (+5 V), at which the TTL LE signals switch the CMOS LE transistors;

2) Use LE TTL with an open collector, the output circuit of which includes a resistor connected to an additional voltage source (Figure 20b).

During storage and installation, beware of static electricity. Therefore, during storage, the terminals of the microcircuits are electrically connected to each other. They are installed with the power supply switched off, and the use of bracelets is mandatory, with the help of which the electricians’ body is connected to the ground.

CMOS-series LEs are widely used in the construction of low- and medium-speed low-cost digital devices. The parameters of some series of CMOS type LEs are given in Table 8.

Table 8 Parameters of some series of CMOS type LE

Options	series
	176, 561, 564	1554
Supply voltage U PIT, IN	3…15	2…6
Output voltages, V:
low level U 0 EXIT	<0,05	<0,1
high level U 1 EXIT	U PIT–0,05	U PIT–0,01
Average signal delay time, ns:
For U PIT=5V	60	3,5
For U PIT=10 V	20	-
Permissible interference voltage, V	0,3 U PIT	-
Power consumption in static mode, mW/case	0,1	0,1…0,5
Input voltage, V	0,5…(U PIT+0.5 V)	0,5…(U PIT+0.5 V)
Output currents, mA	1…2,6	>2,4
Power consumption at switching frequency f=1 MHz, U PIT=10 V, C n=50 pf, mW/case	20	-
Clock frequency, MHz	-	150